1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly the present invention relates to a MOS transistor and a method of fabricating the same.
2. Description of Related Art
In general, a conventional MOS transistor is a kind of field effect transistor (“FET”). The MOS transistor includes source and drain regions formed on a semiconductor substrate. A gate oxide film and a gate region are formed on the semiconductor substrate. In the MOS transistor, metal wires are connected to upper portions of the source region, the drain region and the gate region. The metal wires apply electrical signals to each of the source region, drain region, and gate region, to thereby operate the MOS transistor. These regions function as electrodes.
Techniques related to this are disclosed in U.S. Pat. Nos. 6,541,859, 6,504,224, 6,475,865, and 6,365,468.
FIG. 1 is a sectional view of a conventional MOS transistor. A silicon wafer 1 functions as a semiconductor substrate. A gate oxide film 2 having a predetermined width is formed on the wafer 1. A polysilicon layer 3 to be used as a gate electrode is formed on the gate oxide film 2 and a surface of active region of the silicon wafer 1. A P or N-typed dopant of light concentration is then injected into the silicon wafer 1 at the active region using the polysilicon layer 3 as a mask to form a lightly doped drain (“LDD”) 4 on the silicon wafer 1 at the active region, as shown in FIG. 1. Much of the polysilicon layer 3 is removed leaving the gate electrode 3 on top of the gate oxide film 2. Side walls 5 are then formed adjacent the gate electrode 3, as shown in FIG. 1. Next, after side walls 5 are formed on both sides of the polysilicon layer 3 source and drain electrodes are formed under the lightly doped drain 4, as shown in FIG. 1. The electrodes are formed by injecting dopant having a heavy concentration, which has the same conductivity as the LDD 4, into the silicon wafer 1 at the active region. The source and drain electrodes 6 are formed on the silicon wafer 1 at the active region.
This conventional MOS transistor has drawbacks. There are structural limits associated with miniaturizing these transistors. As such, these transistors are not well suited for the current downsizing or miniaturizing trend associated with the high integration of the semiconductor devices.
Therefore, there is a need for a MOS transistor having a new structure that is suitable for use in today's small, highly integrated semiconductor devices. There is also a need for a fabrication method thereof.